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Manufacturing / Electrical Engineers
Senior/Lead ASIC Verification Engineers Full Time
Exp : 3 yrs to 10 years
· Associated with Verification especially using industry-standard protocols & methodology
· Languages: Hands-on experience with System Verilog & Verilog. Should have a good understanding of Object-Oriented Programming and PCIE ethernet knowledge.
· Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies.