FPGA Verification
Experience – 3 to 10 yrs
Job Description
– Verification of RTL designs – Block/subsystem/chip level functional verification – Implement verification environment independently in SV using UVM methodology – Feature extraction and coverage have driven verification plan development – Development and execution of test cases – Report test results and assist in RTL debug using simulation
Skills
FPGA/CPLD coding, UVM
Exp : 3 yrs to 10 years · Associated with Verification especially using industry-standard protocols & methodology · Languages: Hands-on experience with System...
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